1. Field of the Invention
This invention relates to an interconnect system for wafer scale integrated circuits and more particularly to a power interconnect system employed with a network of circuits on the wafer such as processors, memories, and other devices.
2. Description of the Prior Art
Increasing attention has been given in the prior art to wafer scale integrated circuits as evidenced by the Canning et al U.S. Pat. No. 3,641,661, the Cook U.S. Pat. No. 3,810,301, and the Kilby U.S. Pat. No. 3,835,530.
Signal propagation in any circuit is limited by the velocity of electromatic waves in the conductor medium and, theoretically, by the speed of light. Switching speeds in today's integrated circuits are approaching one nanosecond, during which time the distance over which the signal propagation occurs is approximately 15 centimeters in a printed circuit board. To achieve faster switching speeds, or conversely smaller signal propagation times, it has been recognized that the interconnections between the respective circuits and components must be significantly shorter. This is achieved by wafer scale integration where a large number of discrete circuits are interconnected on a single crystalline substrate, as distinct from the current practice of forming such circuits on individual dice which are then separately packaged and mounted on a printed circuit board.
Wafer scale integration has the advantage of increased wiring densities compared to printed circuit boards as well as a reduction in the number of circuit interconnections required between the respective dice or chips and also a reduction in the number of handling and packaging steps for such chips.
A particular concern in regard to wafer scale integrated circuits is that of manufacturing yield. With today's production processes, about 30 percent of the integrated circuit dice or chips are found to be defect-free and viable. As the size of the chips increase, the probability of defects also increases, thereby reducing production yield. Thus, wafer scale integrated circuits would have to employ a large number of redundant circuits with each circuit occupying as small a proportion of the wafer as possible. After most of the fabrication steps of the wafer, but before the metallization or interconnection step, each of the individual circuits is tested to see if it is in working order and, then, only viable circuits are interconnected by specially created masks during the final metallization step. Such techniques are disclosed in Hoff, Jr. U.S. Pat. No. 4,007,452. Another approach has been to interconnect all the circuits or chips and then destroy connections to defective chips.
With the approach of wafer scale integration, it has been recognized that a number of different circuits or subsystems required for any particular system can be implemented on such an integrated circuit wafer and, in fact, a number of redundant circuits or subsystems can be implemented for later connection to create a plurality of such systems as required by the demand for such systems and the resources available. Such subsystems could be interconnected during fabrication as described above and selected or assigned to a particular system by various addressing techniques to create a parent system that could then expand or contract as required by the particular task that was being performed. For example, a tree-like network could be obtained by starting with one device which is arbitrarily designated at the top and connected to the external world. All end results are reported up the tree to the external world. Additional devices would be addressed for connection to this "parent", and in turn would have downward connections to their children.
However, it is difficult, with a rigid tree-type system, to map a problem onto the actual physical system in a manner that does not leave a large portion of the devices on one side of the physical tree in an un-utilized state. It may turn out that the parallelism is skewed and tends to push the problem onto only one side of the tree with the rest of the actual physical resources not being used. It is desirable, of course, to utilize as many resources as available as fully as possible on any given problem or task, and to have networks that can expand or contract as required.
A particular problem with a tree-type network is that if one of the devices somewhere in the tree were to fail, it cuts off communication to its children and their children and so on down the tree. it is possible that a plurality of different types of detection techniques or diagnostic means can be provided so as to determine, during the running of a particular task or problem, if in fact any particular device is unusable and to alter the network so as to maintain the network in a viable condition. However, any results that were in the system at the time of a particular device failure would be lost. Therefore, it is desirable to have a network that could be rearranged to exclude the failed device.
While communications between the various devices of the architectures described above can be initiated and terminated by various addressing techniques, there is still the problem in a wafer scale integrated circuit of disconnecting power to the failed circuits or subsystems. Although such failed circuits or devices would no longer be employed in the working network, they would still constitute a power drain as well as contribute to the heat dissipation problems associated with such a wafer scale integrated circuit.
It is, then, an object of the present invention to provide an interconnect scheme for disconnecting power leads to various devices in a wafer scale integrated circuit.
It is another object of the present invention to provide a wafer scale implemented system, the various circuits of which can be disconnected after the system has been packaged and placed in use.
It is still a further object of the present invention to provide a wafer scale implemented system in which circuits can be connected or disconnected to expand or contract the system as desired.